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Mirzafer K. Abatchev, Ph. D.

e-mail: plasmaetch@cableone.net
Boise, ID, USA

SKILLS:

Technical leadership; creative and innovative; broad and deep technical expertise in plasma etch physics and chemistry, plasma diagnostics; dry etch process development for various materials in the area of Semiconductor Technology, Nanotechnology and MEMS; design and specification of hard mask layer for advanced patterning; technology transfer, Chamber Matching: procedures including Equipment and Process aspects; Statistical Methods (DOE): JMP, Minitab; Programming languages: Fortran, Matlab, Scilab; Photolithography simulation: Solid-E ; Web page: HTML.

EXPERIENCE:

OrganizationPositionWhenDetails
Lam Research Senior Staff Engineer 2010-present TSV etch development for 3D IC applications
Western DigitalSenior Staff Engineer 2009-2010 Development of processes and process flows to make integrated optical elements
Seagate TechnologyStaff Engineer 2007-2009 MLR application for MEMS patterning
Micron Technology, Inc.Senior Engineer 1997-2007 Plasma etch processes development for new generation DRAM and FLASH memory
Samsung ElectronicsManager/Researcher 1994-1997 Research and development of plasma etch technology
Research Institute Submicron,
Zelenograd, Moscow, Russia
Senior Researcher1992-1994 Development of time resolved mulicannel OES for plasma etch reactor optimization and EP detection
Institute of Physics and Technology,
USSR Academy of Sciences, Moscow, Russia.
Staff Researcher1991-1992 Development of simulation model and writing FORTRAN code for etch profile simulation
Scientific Research Institute for Molecular Electronics and Mikron Factory,
Zelenograd, Moscow, Russia.
Junior Researcher1989-1991 Study of etch performance of high pressure RIE system
Moscow Institute of Physics and Technology,
Dolgoprudny, Moscow, Russia.
Student1981-1989 Physics, Ph. D. (Solid State Electronics and Microelectronics)
Publications More than 50 publications
Miscellaneous Other activities and personal notes

Lam Research, Senior Staff Engineer, 2010-present

Through-Silicon Vias (TSV) etch development for 3D Integrated Circuit applications.

Western Didital, Senior Staff Engineer - Product Design, 2009-2010

Development of processes and process flows to make integrated optical elements for next generation Hard Drive (HAMR - Heat Assisted Magnetic Recording).

Seagate Technology, Staff Engineer, 2007-2009

Proposed process flow which uses a multilayer resist materials that reduces process steps compare with existing process flow and developed plasma etch process to etch the proposed stack (high aspect ratio features with ~1.7 micron - 2.5 micron thick underlayer) in different type etch systems (Anelva, Plasmatherm). This new process flow reduced defects, improved CD uniformity, and increased yield of magnetic recording head for Hard Drives.

Worked with etch equipments supplier to resolve issues and improve plasma etchers for MEMS applications. Found serious problems in the design of the etch chamber.

Micron Technology, Inc., Senior Engineer, 1997-2007

Was a key team player on advanced strategic projects:

  • Proposed the process flow (stack, materials and process sequences) and developed most dry etch processes to make small (sub- 50nm) features at a pitch less than 100nm that enabled earlier development of 50nm NAND FLASH in year of 2004. The result of this project was more than $1,000,000,000 in investments by Intel in IM Flash Technologies (IMFT is a joint venture of Micron Technology and Intel to produce NAND flash memory). Micron Technology uses this technique for manufacturing of 34nm chip (the highest density monolithic multi-level cell NAND flash chip the industry has seen in 2009). I am the co-author of few key patents on this method.
  • Developed critical etch processes for double patterning of cell container (DRAM)
  • Multi-layer resist and a-Carbon HM etch for fine patterning of small (35nm-150nm) features. From the very first wafer until transfer to production, individually managed projects and developed a-Carbon and MLR etch process on different etch tools (Applied Materials and LAM Research) for most critical etch levels at Micron Technology, Inc.
  • Developed high-k dielectric materials etch processes for NAND FLASH memory applications.
  • Developed STI etch process with X+Y gas mixture. Micron Technology uses this process with some minor changes for production of many generations of DRAM and FLASH memory.

Developed and optimized Dry Etch processes for manufacturing of DRAM and FLASH memory chips:
  • - STI etch
  • - Gate etch
  • - Silicon Oxide etch
  • - Metal etch
  • - MLR and a-C hard mask etch
  • - Resist trim
  • - Line edge roughness (LER) improvement

Investigated plasma induced damage caused by differential charging of a wafer surface during plasma processing of dielectric materials.

Solved many problems related with an etch process drift and matching of chambers. Hands on experience with different types of plasma etchers (AMAT, LAM and TEL)

Investigated the effect of aberrations of lenses on degradation of the aerial image of structures. Zernike aberration theory was applied to understand the impact of different types of aberrations (spherical, coma, astigmatism, 3-foil, etc.) on printing performance of the lithographic system. The result of this simulation was used to explain poor printing performance of some steppers in the FAB. Studied the sensitivity to aberrations at printing of 45nm features with next generation optical lithography systems (immersion lithography at NA=1.35). Have experience with lithography simulation software SOLID-E (developed by SIGMA-C and SYNOPSYS).

Samsung Electronics, South Korea; Manager/Researcher, 1994-1997

Investigated different aspects and problems related with silicon oxide etch processes:

  • Etch mechanism in a fluorocarbon containing plasma,
  • Microscopic etch uniformity (RIE Lag and microloading effect)
  • Etch stop problems.
  • Differential surface charging.

Investigated kinetics of a pulse modulated plasma using time-resolved optical actinometry.

Consulted process development engineers in the area of dry etch and plasma diagnostics.

Research Institute Submicron, Zelenograd, Moscow, Russia; Senior Researcher, 1992-1994

Worked on application of acoustooptical (multi-channel) emission spectrometer for plasma diagnostics, plasma etch reactor optimization and etch endpoint detection.

Investigation of F and H kinetics in radio frequency discharges using time-resolved optical actinometry.

Institute of Physics and Technology,USSR Academy of Sciences, Moscow, Russia; Staff Researcher, 1991-1992

Developed FORTRAN code to simulate a trench profile evolution during dry etch process.

For the first time simulation of the etch profile evolution was performed by combining the Monte-Carlo test particle and Fredholm integral equations methods.

Scientific Research Institute for Molecular Electronics and Mikron Factory, Zelenograd, Moscow, Russia; Junior Researcher, 1989-1991

Investigated the etch performance of a high pressure (~1 Torr) narrow gap plasma etch system (RIE).

Moscow Institute of Physics and Technology, Department of Physical and Quantum Electronics, Dolgoprudny, Moscow, Russia. 1981-1989

Degrees:
  • Ph.D., Physics (Solid State Electronics and Microelectronics), 1990
    Thesis: Dissertation 'Investigation of a deep trench formation in silicon during plasma-chemical and reactive ion etching processes' was presented and defended in Institute of Physics and Technology of USSR Academy of Sciences (Moscow, Russia).
    Experimentally and theoretically investigated the microscopic etch non-uniformity during dry etch process. For the first time the simulation of 'Aperture effect' (RIE lag, inverse RIE lag) was performed using Fredholm integral equations method.
  • M.Sc., Engineering Physicist, (Honours degree) 1986
    In my M.Sc thesis I investigated effect of ion energy on the thickness of damaged Si layer in the low frequency RIE system.
    Topics of study:
    General physics, Theoretical Mechanics, Quantum Mechanics, The classical Theory of Fields, Statistical Physics, Physical Kinetics, Solid State Physics, Physical Optics, Physics of Semiconductor Devices, Mathematical Analysis, Theory of Functions of Complex Variable, Theory of Ordinary Differential Equations, Theory of Partial Differential Equations, Theory of Probability, Numerical Methods, etc.

Miscellaneous Notes

In 2008 at Seagate Technology I have successfully completed 120 hours 6-SIGMA Business Excellence Brown Belt Operational Training, which is essential for yield enhancement and cost reduction in a production environment


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